Random access memory (RAM) provides fast, cost-effective, volatile storage for computing devices. The Joint Electron Device Engineering Council (JEDEC) provides memory standards for storage devices. DDR4 SDRAM (double data rate fourth generation synchronous dynamic random-access memory) provides higher module density, lower voltage specifications and higher data rate transfer speeds. DDR4 LRDIMM (load reduced dual in-line memory module) technology uses a distributed buffer approach to implement memory bandwidth efficiencies when scaling to higher capacities and data rate transfer speeds.
With the advancement of DDR memory interfaces, the DDR4 memory currently operates at a data rate up to 3.2 gigabits per second. At such data rates, lossy characteristics and signal reflection in a data channel become significant where the received data eye is smaller than the transmitted waveform. Equalization at the receiver is used to compensate for the channel loss and reflection to recover the distorted data input to improve a receiver performance.
It would be desirable to implement single-ended memory signal equalization at power up.